Technology
XCENA collaborates with Samsung to develop MX1 near-memory compute device
The CXL memory expander integrates 3,072 RISC-V cores to reduce host bandwidth bottlenecks for data-heavy workloads.
The short version
- XCENA partnered with Samsung to create the MX1, a Compute Express Link (CXL) device designed to expand host memory and process data near memory.
- Fabricated on Samsung's 4nm process, the chip incorporates 3,072 RISC-V cores, 2 Arm Cortex A53 control cores, and a custom Vector Processing Engine.
- The device supports up to 2 TB of DDR5 memory and offers downstream PCIe 6 lanes to connect SSDs, exposing them as host memory using DRAM as a cache.
- Hardware integration details and full implementation capabilities for host processor cache-snooping remain unconfirmed.
Key facts
- XCENA partnered with Samsung to develop the MX1, a CXL 3.2 and PCIe 6 memory expansion device featuring onboard compute capabilities.[Hacker News]
- The MX1 chip is manufactured using Samsung's 4nm node and contains 3,072 RISC-V cores operating at 1.1 GHz alongside two Arm Cortex A53 cores for control.[Hacker News]
- The device features a Vector Processing Engine that provides approximately 3 TFLOPS of FP32 and FP16 dot product throughput across the chip.[Hacker News]
- The MX1 chip consumes 40W of power, while the full board consumes 90W when populated with four DIMMs.[Hacker News]
- The board features eight downstream PCIe 6 lanes that allow SSDs to be configured in RAID and exposed to the host as memory.[Hacker News]
What remains uncertain
- It is unclear how the device achieves its reported default 16 GB map cache given that its documented 1,024-entry structure with 64 KB pages mathematically covers only 64 MB.[Hacker News]
- It remains unverified whether the MX1 fully utilizes CXL snoop capabilities to manage cache invalidations with host processors.[Hacker News]